alu/cse141L-project
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fixed bugs in synthesis

Browse Source
This commit is contained in:
Arthur Lu 2022-08-13 18:54:10 -07:00
parent 3c77111bfd
commit 0dbd5dbbea
3 changed files with 29 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
RTL/Ctrl.sv
View File

@ -30,8 +30,8 @@ module Ctrl #(
assign I_Immediate = Instruction[7:0]; assign I_Immediate = Instruction[7:0];
assign T_Immediate = Instruction[2:0]; assign T_Immediate = Instruction[2:0];
assign A_operand = Instruction[3:0]; assign A_operand = Instruction[3:0];
assign S_operand = {'b1, Instruction[2:0]}; assign S_operand = {1'b1, Instruction[2:0]};
assign G_operand = {'b0, Instruction[2:0]}; assign G_operand = {1'b0, Instruction[2:0]};
assign ALU_B = RegOutB; assign ALU_B = RegOutB;

12
RTL/top_level.sv
View File

@ -27,9 +27,9 @@ module top_level(
logic Done_out; logic Done_out;
logic [T-1:0] ProgCtr; logic [T-1:0] ProgCtr;
Ctrl #() control (.*); Ctrl control (.*);
ALU #() alu ( ALU alu (
.A(ALU_A), .A(ALU_A),
.B(ALU_B), .B(ALU_B),
.ALU_OP(ALU_OP), .ALU_OP(ALU_OP),
@ -37,7 +37,7 @@ module top_level(
.Zero(Zero_in) .Zero(Zero_in)
); );
InstFetch #() pc ( InstFetch pc (
.Clk(clk), .Clk(clk),
.Reset(init), .Reset(init),
.BranchEZ(BranchEZ), .BranchEZ(BranchEZ),
@ -50,7 +50,7 @@ module top_level(
.ProgCtr_p4(ProgCtr_p4) .ProgCtr_p4(ProgCtr_p4)
); );
RegFile #() regfile ( RegFile regfile (
.Clk(clk), .Clk(clk),
.Reset(init), .Reset(init),
.WriteEn(RegWrite), .WriteEn(RegWrite),
@ -67,7 +67,7 @@ module top_level(
.Done_out(Done_out) .Done_out(Done_out)
); );
DataMem #() datamem ( DataMem datamem (
.Clk(clk), .Clk(clk),
.Reset(init), .Reset(init),
.WriteEn(write_mem), .WriteEn(write_mem),
@ -76,7 +76,7 @@ module top_level(
.DataOut(mem_out) .DataOut(mem_out)
); );
InstROM #() rom ( InstROM rom (
.InstAddress(ProgCtr), .InstAddress(ProgCtr),
.InstOut(Instruction) .InstOut(Instruction)
); );