36 lines
903 B
Systemverilog
36 lines
903 B
Systemverilog
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// skeletal starter code top level of your DUT
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module top_level(
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input clk, init, req,
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output logic ack);
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logic mem_wen;
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logic[7:0] mem_addr,
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mem_in,
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mem_out;
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logic[11:0] pctr; // temporary program counter
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// populate with program counter, instruction ROM, reg_file (if used),
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// accumulator (if used),
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DataMem DM(.Clk (clk),
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.Reset (init),
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.WriteEn (mem_wen),
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.DataAddress (mem_addr),
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.DataIn (mem_in),
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.DataOut (mem_out));
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// temporary circuit to provide ack (done) flag to test bench
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// remove or greatly increase the match value once you get a
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// proper ack
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always @(posedge clk)
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if(init || req)
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pctr <= 'h0;
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else
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pctr <= pctr+'h1;
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assign ack = pctr=='h256; // pctr needed to trigger ack (arbitary time)
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endmodule
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